As an update, I found some settings in a qsf file on the intel github page. Some key differences I think I have found are in the FPGA device numbers:
From Intel Github qsf:
#############################################################
# Device setup
#############################################################
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE 1SG280LU3F50E3VG
From board package:
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE 1SG280LU2F50E2VG
and in the VID settings:
From the Intel Github qsf:
#############################################################
# VID
#############################################################
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
and from memory the board package had the same settings in the Quartus project but the slave device 0 address being either 55 or 5F.
Would these discrepancies be the cause of my compiling/programming issues? Is there any other settings other than pin assignments that need to be addressed before compiling the .sof files (no IP cores involved)?
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