New ContributorHey,
I've connected an external host functioning as an SPI Master to the DE10-Lite board to communicate with the MAX10 FPGA, which acts as a slave. I’m looking for example C code or an API library that can be used as an external host, acting as an SPI master to communicate with the DUT.
Thanks for your help,
Ofir
Frequent ContributorHi,
Please refer below link for SPI master designs.
Regards
Tiwari
Frequent ContributorHi,
Please let me know if you have any query on this.
Regards
Tiwari
New ContributorOur use case requires the MAX10 FPGA to function as an SPI slave, with an external host acting as the SPI master. We are currently testing this on a MAX10 FPGA using the DE10-Lite board. The SPI signals are connected through the JP3 header, specifically using Arduino_IO0, Arduino_IO1, Arduino_IO2, and Arduino_IO3.
On the master side, we have configured the SPI clock to 1 MHz, with CPHA = 1 and CPOL = 0, as specified in the datasheet. We are sending the following write transaction from the master (writing 0x11223344 to address 0x00000054
7A 7C 00 00 00 00 04 00 00 00 54 44 33 22 7B 11
While we can correctly observe the MOSI, CLK, and CS signals, we noticed that signal propagation appears to be causing issues. Specifically, the first bit in the wrshiftreg samples as 1 instead of 0. Despite multiple attempts to troubleshoot, the signals seem to be getting corrupted at some point (this example is only one issue we've encountered).
Could you confirm whether the SPI-AVMM design is expected to work as intended? Are you aware of any known issues with this IP? If the design should function correctly, could you provide an example project, including the necessary design files, that we can test in our lab? We are currently facing difficulties with the SPI-AVMM IP and would appreciate any guidance you can offer.
Looking forward to your support.
Best regards,
Ofir.
New Contributor
Frequent ContributorAs we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Frequent ContributorHi,
You can try below link on the SPI mode 1 & 3 for SPI slave.
https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/NIOS-II-SPI-Slave-Issue/td-p/1393019
| SPI Mode | CPOL | CPHA | Shift Sclk edge | Capture Sclk edge |
| 0 | 0 | 0 | Falling (negedge) | Rising (posedge) |
| 1 | 0 | 1 | Rising (posedge) | Falling (negedge) |
| 2 | 1 | 0 | Rising (posedge) | Falling (negedge) |
| 3 | 1 | 1 | Falling (negedge) | Rising (posedge) |
Regards
Tiwari
Frequent ContributorHi
Let me know if you have any question on this.
Regards
Tiwari
