--- Quote Start ---
i don't have any idea how to implement button debouncing.
--- Quote End ---
When I debounce signals, I use a small statemachine and registers. I have the code in VHDL, not Verilog, so I'll just describe it.
1) Synchronize the button to the local clock using dual-DFF synchronizer.
Lets call this signal 'button_sync'
2) Delay the synchronized signal using a single DFF
Lets call this signal 'button_delay'
3) Define a signal that is the XOR of these two signals
assign button_change = button_delay ^ button_sync;
This signal will be high when there is a change in logic level.
4) Use a state machine and a counter to control a 'button_debounce' register.
When the 'button_change' signal asserts, the state machine transitions from IDLE to the CHANGE state. On the transition load a counter with the debounce time (use a down-counter, so that carry-out can be used to detect termination). While in the CHANGE state, enable the counter.
If the change signal asserts while in the CHANGE state, then reload the counter. Only when the timer terminates do you update the 'button_debounce' output. This logic ensures that the signal is in a valid asserted or deasserted state for
at least the debounce time.
Create a testbench for your debounce component, and edit/debug until you can debounce a signal.
The above description should get you most of the way there.
If you have trouble, I'll post the VHDL code and its testbench. You can use that as the reference.
Cheers,
Dave
Honored Contributor
