Signals in VHDL

I need to convert a C function to a vhdl code. In the C function there is an array uint32_t a[20] and I convert it to a signal in vhdl (type array_type is array (0 to 19) of std_logic_vector(31 downto 0); ). I made a FSM for this implementation and the problem is when I try to assign some values to the array (a(i) <= some_value;),

However, when I check in simulation (waveform), all values remain 'X', even after a few clock cycles.
What could be the reason for this behavior?

Additional details:

• i is properly incremented.

• The value assigned (some_value) is well-defined (not 'X').

• The FSM transitions correctly through states.

• I have tried using an initialization process for a, but still get 'X'.

Any ideas on what could be wrong?