--- Quote Start ---
I intend to communicate through the dedicated USB lines in the MAX II and not the JTAG lines. Is there any code for configuring from the host(PC) in order to facilitate the USB data transmission from PC to FPGA and vice versa, by configuring the MAX II(USB BLaster II) or should the MAX II firmware be modified.
--- Quote End ---
I'd follow Wombat's advice on this one :)
The USB-Blaster II is a weird beast; Altera have used a Cypress PHY that could have implemented both the JTAG interface and the parallel interface (FPGA4U do it that way,
http://fpga4u.epfl.ch/wiki/fx2), there is no need for the MAX II.
Good luck with your testing. Feel free to write up some notes and post them to the wiki to help others.
Cheers,
Dave
Honored Contributor
