Agilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)

Resolved -- and yes, the EMIF Calibration IP works perfectly for runtime IOPLL reconfiguration on Agilex 5. The problem was the PLL landing on an HVIO site instead of an HSIO one.

The key is in Error(175005): Could not find a location with: HVIO_IOPLL. The reconfigurable IOPLL + pll_calbus + EMIF Calibration IP flow requires the PLL to be placed on an HSIO IOPLL site. The Fitter was only finding HVIO PLL sites for it, and an HVIO PLL site cannot pair with the Calibration IP's hard block -- hence the placement conflict (14566 / 175001 / 16234).

ROOT CAUSE: whether the IOPLL is classified HSIO or HVIO follows from the bank of its reference-clock input pin, not from any IP parameter. In the minimal repro there are no pin constraints, so the Fitter is free to pick an HVIO PLL site for the refclk/PLL -- which then conflicts with the EMIF calbus connection. That is why steps 1-4 place fine and only step 5 (calbus actually wired) fails: it is the first point where the PLL is forced onto a site that must be HSIO, and nothing is steering it there.

FIX: constrain the PLL's reference clock to a pin in a bank that hosts HSIO-capable PLL sites. On the Terasic DE25-Standard, that is CLOCK2_50 = PIN_BM71 (bank 2A_T). The board's other 50 MHz oscillator, CLOCK0_50 = PIN_CH128 (bank 5A), is HVIO-only and reproduces this exact error, identical 6+5 location breakdown. So:

set_location_assignment PIN_BM71 -to <refclk> ;# HSIO-capable bank 2A_T

set_instance_assignment -name IO_STANDARD "1.2-V" -to <refclk>

With the refclk on the HSIO pin, the IOPLL places on an HSIO site, the pll_calbus / pll_calbus_readdata link to the EMIF Calibration IP is legal, the design fits, and runtime C-counter reconfiguration works -- I am using it for dynamic phase shift and getting clean, deterministic 39.06 ps steps on hardware.

ON THE EARLIER COMMENT ("HVIO reconfiguration is done by driving coreavl* directly; EMIF / pll_calbus not required"): that is consistent with this. There are two separate reconfiguration paths -- HVIO PLLs -> core_avl_* directly, and HSIO PLLs -> EMIF Calibration IP + pll_calbus. Error(175005): HVIO_IOPLL is precisely the symptom of trying to use the HSIO (EMIF) flow while the PLL is stuck on an HVIO site. The resolution is to make sure the PLL's bank matches the flow you want: to use the EMIF Calibration IP, put the reference clock on an HSIO bank.

Hope this helps anyone else hitting 175005 with the Calibration IP.