Quartus prime V19: .sdo files not generated for MAX V device, does it still support gate level simulation?

You should still able to generate the .sdo for Max V https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html

Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.. Use Timing Analyzer static timing analysis rather than gate-level timing simulation.

The steps should be here:

To obtain a ModelSim-Altera simulation output file in the Quartus II software, perform the following steps: 1. Choose Open Project (File menu). 2. Select the project and click OK. 3. Choose EDA Tool Settings (Project menu). 4. In the Simulation Tool box: ■ If using ModelSim-Altera, select ModelSim OEM (VHDL/Verilog HDL output from Quartus II). ■ If using Model Technology’s ModelSim, select ModelSim (VHDL/Verilog HDL output from Quartus II). 5. Click OK. 6. Compile the project. 7. The Quartus II output files will be located in the \simulation\modelsim\ directory

You may try Cyclone IV if Max V does not have it, sometimes, it might be documentation error.