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NM11's avatar
NM11
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2 years ago

Power Sequence of Arria V GX (FPGA)

We are using Arria V GX (FPGA) in a prototype we are considering developing. I have 3 technical questions about Power Sequence. 1. In the Arria V Device Datasheet, at the end of Table 3 of 1.1....
lixy's avatar
lixy
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2 years ago

Hi Naoki,


If configuration fails, the FPGA would not fulfill the logic in your design.

When tRAMP requirement of the FPGA device is violated, FPGA would not be able to start Configuration. Even if you find that the FPGA is successfully configured when you violate the requirement in Datasheet, we can not promise all the FPGA devices will work properly in this condition.


Thanks & Regards,

Xiaoyan


  • NM11's avatar
    NM11
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    2 years ago

    Hi Xiaoyan-san,

    Thank you for your reply.
    We changed the design and was able to reduce the ramp time to within 100ms.
    Therefore, I think it is OK since we were able to meet the requirements in the Datasheet.

    Thanks,

    Naoki