Power Sequence of Arria V GX (FPGA)

Hi,

About your first question about ramp time, here's my answer.

A POR event occurs when you power up the Intel Arria V device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP.

As you can see from the Figure 11-7 in the Arria V handbook, POR delay and Configuration time will follow the tRAMP. If tRAMP is not met, the I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.

I will check your second question and see if I can give an answer.

Thanks & Regards,

Xiaoyan