Forum Discussion

Harriet5he's avatar
Harriet5he
Icon for New Contributor rankNew Contributor
4 years ago
Solved

PMBus Configuration and VID setting Error

Hi, I met an Error when programming the Stratix 10 SX FPGA.

it shows the same as @Ppavan mentioned:

1. Error(18950): Device has stopped receiving configuration data
2. Error(18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000B400)
3. Error(20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board.
4. Error(209012): Operation failed
I've followed the solutions following other posts on the user guide, on the checklist and in Intel FDB, but I failed to find out what's wrong. I've tried every pin options about the SDM, and I applied the same regulator as another Stratix 10 product. It doesn't work.
I wonder must I open the server again to check the pins? (Though I've tried every possible combinations of the pins in my "Configuration Pin Options" so I doubt whether it goes wrong in this particular option)
At the same time, I'm not sure how to fix the type of regulator applied on the board, I find its "relative" uses EM2130H, but the software assigned it as LTM4677. Also, if I select "Other" in this option, whether should I enter the particular regulator and if the answer is yes, where could I enter it?

I am using Quartus Prime Pro 19.1

I am using Stratix 10 SX Dev Kit with Device: 1SX280HN2F43E2VG


Thanks for all help!!!

  • Harriet5he's avatar
    Harriet5he
    4 years ago

    OHHH I solved this problem.

    I checked the update package of the d5005 chip and searched for qsf file in openCL hardware manager, and changed power management setting in my project. The core error is a wrong address number of the slave device protected by the openCL interface.

    Thanks very much!

5 Replies

    • Harriet5he's avatar
      Harriet5he
      Icon for New Contributor rankNew Contributor
      4 years ago

      Yes, I tried them as long as I met the error.

      However, the setting in this design is not compatible with the FPGA I want to program onto, so it always fail.

      Then I checked the qsf file in this package and reviewed the setting in my project according but it didn't work, too.

  • Harriet5he's avatar
    Harriet5he
    Icon for New Contributor rankNew Contributor
    4 years ago

    OHHH I solved this problem.

    I checked the update package of the d5005 chip and searched for qsf file in openCL hardware manager, and changed power management setting in my project. The core error is a wrong address number of the slave device protected by the openCL interface.

    Thanks very much!

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    I am glad that to hear that the issue has been resolved.


    • MojoFox's avatar
      MojoFox
      Icon for New Contributor rankNew Contributor
      3 years ago

      I have the same issue with a Stratix 10 Dev Kit. I am so puzzled as to why intel Moderators do not capture the full and detailed solution like Xilinx Answer Records do. That way when others search for this problem and find this they could follow the detailed solution instead of being disappointed that Intel is just happy that Harriet5he found his solution, whatever it is. What about others who have the same issue? I have no idea what the solution is from this thread.