PLL on Altera DE3 Development Board doenst work

That's because if you use the implicit port assignment, the external signals are connected to the component ports depending on the listing order.

Then, according to the definition:

Component PLL is
	PORT(
		inclk0 	: in std_logic;
		c0			: out std_logic;
		locked	: out std_logic
	);
End Component;

when you instantiated PLL_inst : PLL PORT MAP(CLK, OPEN, CLK_100 );

you actually connected c0 to OPEN and locked to CLK_100

Using the explicit assignment is the common practice and it is strongly recommended, since it avoids any confusion, especially when you need to modify the component definition.