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I/O --> FIFO --> mSGDMA --> SDRAM (connected to FPGA) --> mSGDMA --> PCIe --> Host memory
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I think the Datas have not to be stored in SDRAM. Since the FiFo can store more than 8000 data packages.
So I think this will do the trick:
I/O --> FIFO --> mSGDMA --> PCIe --> Host memory
I just have to pick up the Datas very fast. And with the FiFo directly attached ti PCIe (via mSGDMA) I have only one adress where the Data is stored and don't need to build another Storage-Structure in the SDRAM.
(Correct me if I'm talking absolutely bullsh**.)
And I don't have to move the data internally to SDRAM.
The only usable FiFo with MM is the On-Chip FiFo which I have now connected as shown beyond.
The In-Clock will be later exported and connected to the external clock source of my testdevice.
I think with enable bit you mean the "avalonmm_write_slave_write" bit. Can I connect it (externally) to clk_in to automatically trigger writing with 50MHz?
Now there is another problem I don't understand: how do I connect the exported Ports to the HSMC-connectors. Normally I would use my soldering iron but I think my boss will kill me if I start soldering on the board :D.
OK in Pin Planner, but how does it come that there is no Node or something for FiFo to assign a pin to? What must I do to see the FiFo-Ports in Pin Planner?
PS: Don't I need a bridge or something to translate the generic bus into a avalon interface?
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