PIO to Memory to PCIe on Arria II GX

I would eliminate the PIO since it doesn't add anything and just makes the design more complicated. In Qsys just add a FIFO with the write port exported to the top. Wire up your 32-bit data to the writedata signal of the FIFO, drive the enable bit high when you want to sample. For the read port of the FIFO just hook it up to the DMA. You could also make your own FIFO component so that you can enable the sampling using a CSR access (FIFO are one of the easiest components you can create for Qsys so don't let component creation scare you)

The reason why you don't want to sample directly from a PIO is because you can't ensure the time between samples will be constant (you don't know when the master will issue the reads). Working with a constant interval between samples is way less complicated than variable interval data (especially when you don't know what the interval time is). By sampling directly into a FIFO you just have to ensure the DMA can keep up with the sampling rate so that the FIFO doesn't overflow, the interval between samples is handled automatically by the write enable of the FIFO itself. So for what you are trying to do this would be a better data path:

I/O --> FIFO --> mSGDMA --> SDRAM (connected to FPGA) --> mSGDMA --> PCIe --> Host memory

To do this you just need to maintain a pair of descriptors, one for the first transfer into the FPGA local memory and the other to transfer the 32MiB of data to the host. The software with the design already does the latter so you would just need to add the part that does the local buffering (read from FIFO write to SDRAM). How you write that in the host application I have no idea since I'm not familiar with the application or Jungo drivers.