Contributor
Regular ContributorHi David,
Can you specify which link you are looking at ? So that I can provide the new link for you.
For BAR size configuration, I suggest you to refer to
It might not be exact what you looking at as that is AVMM design example. Hope this help.
Regards,
Wincent_Intel
ContributorHi Wincent,
I roughly know how to reconfigure the BAR on the FPGA side. I want to know how to test it on Host PC, for example the Boardtestsystem.exe software. The BAR is predefined by the example FPGA project, if I understand correctly, after I update the BAR content with my application, is there any example/ tutorial to create/update the boardtestsystem.exe software so I can access all memory/register space to test the new FPGA.
now I have a new FPGA on the dev kit board, I need to test it with a customized BTS, I want to know is there any document from Intel to instruct developers to create BTS.
thank you,
David
