Honored Contributor
Honored ContributorI'm half-remembering the diagrams for the (IIRC) avalon streaming interfaces to the PCIe block. I think you can use them instead of the Avalon master interface. I'm sure there are separate tx and rx streams (I might just be thinking of the fpga being a PCIe master).
If I'm remembering correctly then it is likely that the avalon master is built on top of that interface. In which case nothing on the fpga will actually enforce that a write finishes before a read to the same address - even though the actual PCIe cycles have to be ordered. Hmmm... I've just realised you are talking about very long delays between the write and read cycles - not ones that are back to back on the pcie bus.
