Honored Contributor
Honored ContributorI'm going to run simulation on this but I'm not sure if I will be able to repeat the hardware fails ... I may get some insight though.
On the weekend I checked the PCIe Hard IP in QSYS and noticed under "Avalon MM System Settings" the "Single DW completer" is not checked ... checking this takes out the burst count signals from the Avalon MM BAR masters. I can look at the Simulation to see what difference this will make but I expect, it constrains the Master to single DW transfers. It is hard to believe the interconnect can be loosely ordered ... but probing the PCIe BAR1 Avalon MM master will say if the ordering issue is in the PCIe Hard IP or in the Avalon MM interconnect. The other thing is that the write / read test runs fine from the RC prior to starting NIOS II in the Eclipse environment ... after that the test fails. Even if the NIOS II code is just a single printf or even just return(0), I still get the errors. I would like to go into the debugger and see if it fails prior to any instruction execution ie just sitting at the entry point. I have never been able to get the PCIe Compiler to edit the PCIe Hard IP megafunctions even if I edit the .tcl definition to make it editable ... does any one have any experience with that or do we just go with the PCIe Hard IP that comes delivered for each FPGA family. Thanks, Bob.
