PCIe Hard IP returning stale data for Cyclone IV

Thanks DSL,

I made the IMEM mailbox ,which is the shared memory between the NIOS II and the PCIe BAR1 ( read host RC system ), dual_ported.... that is BAR1 -> port 0 and NIOS data -> port 1.

Things improved but not fixed ... now the tests pass from the RC prior to NIOS II code running , same as before .

With NIOS II code running I now have a 2 cycle offset rather than 8 cycle offset between write data from RC and the read data changing. That is after NIOS prints "Hello world" and returns. With NIOS application running , I see a 4 cycle offset ... so improved but not passing with NIOS yet.

I examined the RTL and can't see where in the interconnect there are any FIFO's so it could be some kind of 2:1 arbiter for writes , holding writes off.