PCIe design example for Arria10 SX

Hi,

Any of you familiar with the PCIe design example for Arria10 to help me with the following?

I generated two PCIe design example for Arria10 SX for two different boards (with different Arria10 SX part numbers) using Quartus pro 18.1. I see the following:

• both design pass the simulation test.
• both design fail the same way on HW test. The test shows that read back data is FFFFFFFF, not ABCD1234 as expected.

I use signal tap to look into the rx_st and tx_st buses and I see something strange:

• there is never any activity on the tx_st bus, i.e no tx_st_valid, tx_st_sop, tx_st_eop, tx_st_data.... in other words, there is no data coming back to the host.
• I see some invalid data cycle on rx_st bus, i.e. I see rx_st_valid high but rx_st_sop low and/or rx_st_eop low.
• Once in a while, I see a read cycle on rx_st_data with the data pattern ABCD1234. The read command on rx_st bus (from host to FPGA) should not have any data pattern. Read data should return on the tx_st bus (from FPGA to host). It looks like this is a write command but it is corrupted and becomes a read command.
• Sometime is see an invalid write command with poison bit =1. It looks like a write command is corrupted.

I use Avalon ST, PCIe gen2/3 x4, 64 bit, 250Mhz. The design example seems to target the Arria10 GX development board but I think it should work with Arria SX part on my board since there is no error when i compile for Arria10 SX.

I only have the signals for PCIe bus between the FPGA board and the host. I don't have any of those signals that are available for Arria10 GX development board. This should not be a problem, should it?

Let me know if you want to see some of the waveform on rx_st and tx_st bus. I can capture them and share with you.

Thank you for your help.