On the Arria 10 SoC FPGA Development Kit Board, why is VDDO set to 1.8V for the Si5338 DDR4 clock driver when the DDR4 operates at a lower voltage?

Hi Sir, The reference clock is using LVDS IO standard. Thus, the clock source is 1.8V.

For LVDS input, it is power-up by the VCCPT which is 1.8V. Thus, there are no conflict with the VCCIO.

See this document for the details. Table 33, see note 6.

Input for the SSTL, HSTL, Differential SSTL, Differential HSTL, POD, Differential POD, LVDS, RSDS, Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPT

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf#page=104