Forum Discussion
zyadmohammeed
New Contributor
New ContributorMAXV CPLD I/O problem
Hello,
I have MAX V CPLD there is a problem with the I/O pins when I assign Signal on the I/O some of these I/O fails to out put the signal correctly.
for example, I wrote a dummy Verilog design ...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
Have you done a simulation first with the design? Is it still giving you the same issue?
Regards,
Aqid Ayman
