Forum Discussion

New Contributor

3 years ago

MAXV CPLD I/O problem

Hello, I have MAX V CPLD there is a problem with the I/O pins when I assign Signal on the I/O some of these I/O fails to out put the signal correctly. for example, I wrote a dummy Verilog design ...

Farabi

Regular Contributor

3 years ago

Hello,

Can you share your simple design so I can test with our devkit?

Most of the time, the root cause could be the pin assignment where you assigned a specific pin, but the VCCIO of that pin does not matched with the real VCCIO on board.

regards,

Farabi