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zyadmohammeed's avatar
zyadmohammeed
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4 years ago

MAXV CPLD I/O problem

Hello, I have MAX V CPLD there is a problem with the I/O pins when I assign Signal on the I/O some of these I/O fails to out put the signal correctly. for example, I wrote a dummy Verilog design ...
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,


Can you share your simple design so I can test with our devkit?

Most of the time, the root cause could be the pin assignment where you assigned a specific pin, but the VCCIO of that pin does not matched with the real VCCIO on board.


regards,

Farabi


zyadmohammeed's avatar
zyadmohammeed
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4 years ago

sure Here is our testing design the pins that are not working Pin (7,24,39,48,52,63)

this example should drive high on all the pins