LVDS receiver resistors

Hi smileface, I'm sorry but I don't know how to help you. I haven't got the interfacing to ADC done until now because I've still got problems with the hardware to work on.

Anyway, I think there is nothing much to know about DDR LVDS: the first word means that bits are alternatively sent on each edge of the clock (for my ADS58B18, as it is found on its datasheet, odd bits of each sample are sent on the rising edge of the clock, even bits on the falling one); the second word means that 0 and 1 logic levels are defined with respect to the voltage difference among two pins of the FPGA (which anyway have to support this kind of I/O standard, as it is the case for FPGA pins connected to HSMC connector on my board). So, each of the two things can exist without the other.

I don't know if this is the right choice, but I've tried to implement "manually" the shifting of the input bits in a register (without using the IP you mentioned) and I'm currently simulating my design. If you want, I'll let you know if it works once programmed on the FPGA.

Please some guru correct me if I'm wrong with anything I've said, as this could be of help for me too.

Regards,

Lorenzo

Hi,Lorenzo,

Thank you for your reply.

The interface of ADS58B18 is very similar with the ADS62P29 which also supported DDR LVDS or CMOS level.

why not use altlvds_rx or altddio ?

Did you try to use two register to acquire data triggered by the rising and falling edge and then shift the bits to a register. (integrate the odd and even bit)

Do you use the PLL with the clkout_p and clkout_n from the ADS58B18.

best regards

Alan

Hi Alan,

as I previously said I couldn't verify my firmware yet because of some problems with the hardware, so I can't tell you that my solution works.

Anyway, my point of view is not to use any IP untill you really need it, and since the problem seemed easy to understand and solve for me I tried to do it in VHDL. I still haven't used any PLL for the implementation of that interface, even if I think I will probably have to.

So my answer is: let me try if my solution works and I'll let you know how I did it =)

Regards,

Lorenzo

Hi smileface,

I finally switched to use altddio IP (I'm not sure altlvds_rx fits our needs). I'm still having some problems in getting the right interpretation of what I'm receiving, but at least the devices seem to communicate with each other.

I think that, at the frequency we're dealing with, I/O timing should be important. The following link explains well source-synchronous interfaces: there's also an application example with an ADC from TI in all similar to ours.

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

Regards,

Lorenzo