LVDS receiver resistors

I'm currently developing on a ArriaII EVM together with an HSMC daughter card (TI's ADS62p29EVM through HSMC-ADC-bridge adapter).（that's very similar to your design） I also need to use DDR LVDS for interfacing the cards.

But I'm a freshman with this interface and are confused about DDR LVDS. I want to see the actual waveform using signaltapII.

I added a DDRIO_in megafunction to interfacing the ADC chip.Pin IN[5:0] and INCLK are from ADS62P29 and SIGNAL_TAP_CLK is used in the signaltap clk.

But it can't compile successfully.I got an fitter error:Folling 6 routing resources needed by more than one signal during the last fitting attempt.The 6 pins are IN[5:0].

Do I miss something like sdc or regenerator the INCLK in the PLL module, I really don't know how to find this informations.

Many thx.

Regards,

Alan