Hi,
Some PCIe ref designs may use L-/H-Tile AVMM+ IP. By following the UG (https://www.intel.com/content/www/us/en/docs/programmable/683667/23-4/introduction.html) to understand the IP and its signals, please generate a DMA design based on L-/H-Tile Avalon Memory-Mapped Intel FPGA IP for PCI Express as attached pcie_avmm_qsys_screenshot.png. You can find msi_* output signals in design and the descriptions are in Table 45. This example design is AVMM with External Descriptor Controller. You can find several irq related codes in software/kernel/linux/intel_fpga_pcie_dma.c. It is possible to monitor related variables to understand the function.
In FPGA design, since the msi_intfc is used, it is also possible to monitor its operation.
I am not an expert of driver. The demo you want is very likely already included in the ref design from my view. As suggested above, please trace these variables and signals to check how all these in dealing with interrupts.
Regards,
Rong
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