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Amir3's avatar
Amir3
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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JIC file format - after "Examine" operation , why is "Signal Tap" written?

Hello everyone, In my system, from time to time some of the information in the Flash device goes wrong. When I perform the "Examine" operation through the Programmer, I see that there is a dif...
  • FvM's avatar
    FvM
    4 years ago

    Please notice that the .jic file header isn't read from the flash device rather than generated during programming file conversion respectively when storing the examined file. I don't know where the "Signaltap" text comes from, probably it has to do with the project loaded by Quartus at the time of examine operation. It doesn't tell anything about the .jic content.

    Regards

    Frank

Amir3's avatar
Amir3
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

We store the configuration file (SOF/JIC) in MT25QL256 flash device from start address 0x0.

The FPGA in Active serial mode.

Every ~500 power cycles, the system does not wake up, and after we program the flash device and restart the system, it goes back to work. We understand that we have a memory problem but we don't understand why.

To analyze the problem, we extract the data from the flash device by "Examine" operation.

We are trying to understand why it is written in the text of the extract file "...(V6AF7PBCE1LYS Signal Tap;)..." and not "...Untitled...".

By the way, if we do "Examine" to the system when the problem doesn't appear, we read in the extract file "...Untitled...".