JAM STAPL player for MAX 10 device 10M25DCF256C7G

Forgot to mention that I try to use JAM STAPL player (downloaded from Intel website) implemented to on board processor to configure MAX 10 FPGA.

From the downloaded code, we found some commands and addresses used but no definition could be found. These commands and addresses were listed above.

With downloaded code, we can't get reading ID through (command 0x06 ID_CODE). The TDO bus is flat. However, when we manually sending the command. The ID code is obtained. The only difference is the JAM STAPL Player code has default 5 us delay, the manual command does not. Now I have question about the delay

1) Does the default idle delay parameter in the source code need to modified based on FPGA and Processor speed ( we saw the description in some documents)?

2) If so, Is any reference of timing model related to MAX 10 FPGA and processor speed model or parameter available?

3) All read commands have same delay?

4) What do we need pay attention to write command or erase command?