Forum Discussion
i forgot to mention in my question that,
I am getting this failure with and without the scatter file.
which address of the DDR3 memory should i use in my scatter file.
the scatter file which i am using is mentioned below.
SDRAM 0x02000000 0x02000000 ; 32M SDRAM
{
APP_CODE + 0
{
* (+RO , +RW , +ZI )
}
ARM_LIB_STACKHEAP 0x03000000 EMPTY 0x01000000 ; Application heap and stack
{ }
}
Hi ,
Sorry, I am not sure about DS5 flow as I never used it. But either in .sopcinfo file or device tree file SDRAM offset must be mentioned.
Any software engineer can help to solve this issues.
I would suggest you to post this issue under EDS group to get the answers
https://forums.intel.com/s/topic/0TO0P000000MWkdWAG/intel-soc-fpga-embedded-development-suite
With Regards,
HPB