Internal ESD protection of Arria V.

Hi Sven,

You may refer to our Arria V datasheet for the absolute maximum rating for the I/O:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_51002.pdf (Page 6)

Thank You.

Hi Bruce,

please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_5v2.pdf page 155. There is a optional clampind diode shown. This diode is recommend for

"If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O pins. Use the on-chip clamping diode for the Arria V GX, GT, SX, and ST devices, and an external clamping diode for the Arria V GZ devices."

Where to find the clamping voltage of this diode? Where to find max. voltage and current for clamping event of this diode? Are the values mentioned by you the max. ratings for clamping event?

Its very import for us to find out because of Maximum Allowed Overshoot During Transitions for Arria V Devices in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_51002.pdf page 6.

Depending of AC input voltage the Overshoot event could be taken in account with the optional clamping diode mentioned above.

Many thanks in advance.

Kind regards,

Sven

Hi Sven,

Yes, the value will not exceeding VOL and VOH when it is clamped with clamping diode. To enable this, you will need to enable in pin assignment in Quartus software.

Thank You.

Hi Sooy,

how about an unconfigured/factory programmed FPGA? Are the diodes on or off without a first initial debug?

Regards

Sven

Hi Sven,

During configuration mode, all the I/O pin will be tri-stated with weak pull up. After that, the diodes will turn back based on your setting.

Thank You.