Forum Discussion

Occasional Contributor

2 years ago

Interfacing Nios II and HMC on Cyclone vGT

Hi everyone, Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write int...

KellyJialin_Goh

Frequent Contributor

2 years ago

Hi,

Seems like the issue lies in the memory larger than 256Mb and causes the DDR3 unable to pass through HMC but able to go through Soft Memory Controller.

I will attach the screenshot on the CV GT user guide on the DDR HMC information for your reference: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf

Thank you.

Regards,

Kelly

Aidin-P2D

Occasional Contributor

2 years ago

Thanks Kelly,

something is not adding up here . data sheet says 256MB however, Nios and Platform designer see the memory size of 512MB? could this be a problem? see below from platform designer?

Thanks

Aidin.

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Interfacing Nios II and HMC on Cyclone vGT

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