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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Interfacing Nios II and HMC on Cyclone vGT

Hi everyone, Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write int...
Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Kelly,

Thanks for your follow up and apology for delay from my side. I was out of office. we are confused and surprised with the response you provided about no support on Cyclone V GT series. CV comes with two Hard Memory Controller Support (That is what data sheet says) and we even have design examples from Altera which contains HMC IP core. even Quartus doesn't complain when we instantiate the IP core and the core works fine stand alone when it is not interfaced with NIOS II.

my question is why Intel provides device with HMC design examples with HMC IP core and you are saying that is not supported? we are very confused.

Regards,

Aidin.