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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Interfacing Nios II and HMC on Cyclone vGT

Hi everyone, Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write int...
Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Kelly,

Thanks for your message. I am afraid that didn't work either. do you have more information on how to close DDR3 timing ? do you think this could be the cause of problem? on timing analysis , I can see some warning indicating the timing closure was not achieved.

if you need, I can share more info. This issue is very critical for us and fixing this will save us significant time/cost in project. Thanks for your help again.

Regards,

Aidin.