Intel Agilex 7 HPS A53 core

Hello,

This question is regarding:
Agilex 7 FPGA I-Series Development Kit(ES1 2x R-Tile & 1x F-Tile) DK-DEV-AGI027R1BES(Power Solution 1) AGIB027R29A1E2VR3

Using the instructions from:
https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7
We were able to load u-boot-spl-dtb.bin to the OCRAM (@0xFFE00000) and see the u-boot serial output on teraterm.

I can successfully read/write registers on the A53 core0 but have difficulty with cores 123. I am not sure if core 123 are still being held in reset, or if they are running off in the weeds.

Please help with these specific questions concerning the HPS quad-core cortex-a53:

#1 What is the value of the cores123 RVBAR_EL3 registers? Note for core 0 that RVBAR_EL3 register has a value of 0xFFE00000 which correspond to the OCRAM.

#2 Are the cores 123 released from reset at the same time as core 0?

#3 Usually memory mapped registers exist to release an A53 processor from reset, probably by the MAX10?
Are such registers available to be accessed by A53 core 0?
And is there documentation for these registers?

Assuming that cores 123 also have RVBAR_EL3=0xFFE00000, I have placed firmware in DRAM and tried releasing each core from the u-boot spin table to branch appropriately, but this has not been successful.

Thanks

PS - Some useful documentation here, but nothing that answers above questions:
https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/resource.html
https://www.intel.com/content/www/us/en/support/programmable/support-resources/guided-journey/agilex7/software-development.html