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yu1987-08-22's avatar
yu1987-08-22
Icon for New Contributor rankNew Contributor
3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


On a fresh Platform Designer, after creating a new .qsys file, can you share the whole steps you did from adding the IP to any changes, connections, export etc. that you did. We need the full list since I am not seeing the issue what you seeing.


As a matter of fact, please see how our GHRD connection is done:

https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD


What is your objective that you made such connection anyway? We recommend that you use the GHRD and you may remove any unwanted IPs or change an default settings then proceed from there.