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yu1987-08-22's avatar
yu1987-08-22
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3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I am still not seeing what you are seeing.


Can you list all the settings/changes you made once you select the HPS Agilex IP from the IP catalog to Generating the HDL in Platform Designer:




yu1987-08-22's avatar
yu1987-08-22
Icon for New Contributor rankNew Contributor
3 years ago

Hi ,

Please see my whole project.

BTW: Whether it's license problem or not？