Forum Discussion
yu1987-08-22
New Contributor
New ContributorHPS(Hard Process system) generate Verilog for Simulation
Hi All,
Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks
Please see the following picture.
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yu1987-08-22New Contributor
New ContributorHi,
I have got no errors during compilation,(Quartus prime pro eition 22.2).
I also send you my project file(please check the attachment) ,you can open project in your local place. please help me double check.
Which file in your project did you check that stated the value is 0?
answer: you can grep the fpga_interfaces in your generation IP file. because different generation, maybe different file names, but instantiation name is always fpga_interface.
yu1987-08-22New Contributor
New ContributorHi，
Please see the attachment， I have send the whole project. You can open in your local place. Thanks
