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yu1987-08-22's avatar
yu1987-08-22
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3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
sstrell's avatar
sstrell
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3 years ago

You should be looking for H2F, not S2F, as the port to connect to. Can you show more of the parameter settings and code?

Not sure what device you are using, but "S" I think is the connection to the hardened SDRAM controller in Cyclone V and Arria V SoC (it's been a while since I've looked at them).