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2258432's avatar
2258432
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

How to use HPS Ethernet to transmit FPGA generated data to another board

I'm a beginner who has just started working with SOC_FPGA. I'm using two DE10-nano boards and I want to generate video color bars on one board and then transfer them to the another board through Ethe...
  • Jeet14's avatar
    Jeet14
    2 years ago

    Hi,


    You need to transfer data from FPGA to HPS DDR memory using the DMA or FIFO and the F2H bridge. This will be in your Verilog code.


    In software linux, you need to write the linux userspace code for reading data from DDR and fill the buffer and send over HPS ethernet.

    For ethernet in linux you need to write the socket programming to build the TCP/IP or UDP application over ethernet for server or client on board.

    We don't have this example code but it is generic way of writing the linux TCP/IP app. For reference you can refer below link

    https://www.geeksforgeeks.org/tcp-server-client-implementation-in-c/


    For HPS & FPGA data transfer, please refer the below link.

    https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM_basic


    Let me know if you have any other query on this topic.


    Regards

    Tiwari


Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


You need to transfer data from FPGA to HPS DDR memory using the DMA or FIFO and the F2H bridge. This will be in your Verilog code.


In software linux, you need to write the linux userspace code for reading data from DDR and fill the buffer and send over HPS ethernet.

For ethernet in linux you need to write the socket programming to build the TCP/IP or UDP application over ethernet for server or client on board.

We don't have this example code but it is generic way of writing the linux TCP/IP app. For reference you can refer below link

https://www.geeksforgeeks.org/tcp-server-client-implementation-in-c/


For HPS & FPGA data transfer, please refer the below link.

https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM_basic


Let me know if you have any other query on this topic.


Regards

Tiwari


  • 2258432's avatar
    2258432
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I am using FIFO and AXI Bridge, where s0 of AXI Bridge is connected to H2F AXI Master, and m0 is connected to the output of FIFO as shown in the figure. Since AXI Bridge s0 is in Avalon-MM Slave mode, it cannot be connected to F2H AXI Slave, so I can only connect it to H2F AXI Master. If I connect it as shown in the picture, will it still be possible to read data correctly from the HPS side?

    Thanks.