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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

How to start and run a baremetal aplication without the debug

Hi, I've managed to debug my code and now I want to test it on FPGA side. The issue is my board (cyclone V soc dev kit) has only one uart to Jtag yet I need to monitor the FPGA and HPS at the same ...
Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


0x01000040 is to load or run your application from the DDR.

0x00200000 is to resize your stack size for application on DDR.


This depend on your design and user config for selection the different partition like .stack, .heap, .ro, .data, .text, etc in you application linker script.


And, I believe your original query has been answered and resolved. With that, I now transition this thread to community support.


If you have any other query then I suggest you to post new case on the forum, we will assist you further.

Thank you.


Best Regards,

Tiwari


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.



  • CAlex's avatar
    CAlex
    Icon for Contributor rankContributor
    2 years ago

    Hi,

    I made a helloworld code and compiled it as you said,

    but the image didnt print any thing:

    "

    U-Boot SPL 2020.07-08705-g35d7cfb999-dirty (Jun 28 2023 - 19:53:47 +0800)
    DDRCAL: Scrubbing ECC RAM (1024 MiB).
    DDRCAL: SDRAM-ECC initialized success with 579 ms
    Trying to boot from MMC1

    U-Boot SPL 2020.07-08705-g35d7cfb999-dirty (Jun 28 2023 - 19:53:47 +0800)
    DDRCAL: Scrubbing ECC RAM (1024 MiB).
    DDRCAL: SDRAM-ECC initialized success with 579 ms
    Trying to boot from MMC1

    U-Boot SPL 2020.07-08705-g35d7cfb999-dirty (Jun 28 2023 - 19:53:47 +0800)
    DDRCAL: Scrubbing ECC RAM (1024 MiB).
    DDRCAL: SDRAM-ECC initialized success with 579 ms
    Trying to boot from MMC1

    "

    Do you know how to solve it?

    Reguards.