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jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

How to recompile verilog code with slight change in reg value using previous fitter(Place & route)

I have a working compilation with the Fitter (Place & route) generated by Quartus 18.1. When i change a value in a 32bits register from assign PROD_VERSION = 32'h0008_0008; to assign PROD_VE...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Are you referring to the first compile after the design partition? If so, then yes.

The subsequent recompile should remain/no change.

You may checkout the KDB on what may cause the compilation results changes.

https://www.intel.com/content/www/us/en/support/programmable/articles/000084189.html

Also, it mentions that "the first compilation after turning on a preservation option may have different results than the previous compilation for portions of the design that are not preserved. Subsequent compilations with no changes will be identical."

Hope that clarify.

Best Regards,

Richard Tan