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jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

How to recompile verilog code with slight change in reg value using previous fitter(Place & route)

I have a working compilation with the Fitter (Place & route) generated by Quartus 18.1. When i change a value in a 32bits register from assign PROD_VERSION = 32'h0008_0008; to assign PROD_VE...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Quartus is not able to rerun full compilation a design without running fitter.

https://www.intel.com/content/www/us/en/support/programmable/articles/000084189.html


You can design partition and preserve the fitter(final) database, a portion of the design. Instead of the whole design undergo P&R.

https://www.intel.com/content/www/us/en/docs/programmable/683247/19-4/design-partitioning.html


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.



  • jkhoo's avatar
    jkhoo
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    HI Richard,

    Thanks for the guidance, will try out your suggestion.

    from JJ