How to convert Cyclone III Verilog files to Cyclone V?

I have an old FPGA board running on Cyclone III which has Verilog files but doesn't have any bdf, so it was difficult tracking the connections. Now I want to rewrite the programs for the new Cyclone V (Terasic DE0 Nano-SoC) board that I purchased. However, the Cyclone III code uses ftdi-usb communication and the new board uses Virtual JTAG communication. So the format of the code are mostly different. Also, the cyclone III code uses .qip files along with Verilog files. How should I go about rewriting this code and what factors must I consider while doing this? Any advice would be greatly appreciated.