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Dear irun2,
EP2C35 is not a cpu but an FPGA. You could of course design cpu's inside.
The maximum speed of circuits in FPGA's depends on their design, the depth of the logic and the interconnection. You can make estimates of the timing performance by means of the Quartus-II tool called "Classic Timing Analyzer" which is simple to use and gets you a reasonable estimate. If you want more accurate timing analysis you can use better constraints and get more accurate estimates by the TimeQuest tool.
When designing circuits you can get higher speeds by keeping the combinatorial logic depth low. This can be done by making pipelined designs.
So it depends.
For small circuits you should be able to get speeds over 200MHz.
For more complicated circuits it could be that you only get 100MHz or even lower.
It depends on the cleverness and complexity of your design.
hope this helps...
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Thanks for your detailed explanation!
But i still have one concern, say when dealing with a SPI interface design in DE2, from the timing analyse report we get the speed the device EP2Cxx can run, but how do we know if it's safe and stable when it's running on the board? I guess somewhat it's related to the board's design...
Pleas kindly correct me if I am wrong! ;)
Honored Contributor
