FPGA Cyclone V cold boot -> crash / Soft reset ok => please help!

Hi qwitza,

Sorry for the delay, with your detailed description, from what I see this is mainly on the cold boot side and not warm reset, thus I suspect the FPGA fabric or the clock side/clock are not fully stable or still in reset state when bridge enable command is given.

to quickly test:

bridge disable
ext4load mmc 0:2 ${loadaddr} ${fpgafile}
fpga load 0 ${loadaddr} ${filesize}

//just to check whether really is timing racing condition issue, for now just delay 5sec, when you mentioned wait long time , how long roughly the time, some few seconds long? just for testing wait 5 seconds or more just to really drill down to timing condition

sleep 5

bridge enable
mw 0xff200000 0x1

When enabling bridges after cold reset, the recommended sequence is:

Wait for FPGA configuration done (nCONFIG/nSTATUS, or FPGA Manager state machine in U‑Boot/Linux)
Release FPGA–HPS interface resets via Reset Manager
Enable bridge control bits
Access FPGA peripherals

For warm reset, some of the reset sequencing are not needed thus in this case , why warm reset no issues but cold reset intermittently having issue. Is this issue occur on a particular board, or multiple or all boards that you have?

Thanks

Regards

Kian