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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

FFT IP simulation errors in modelsim

Hi,

I am trying to use FFT IP in Intel Quartus 18.1. The IP catalog opens a platform designer window for selecting the parameters. It generates a FFT folder in which the related files and pkg files are present.

When I tired to simulate the IP separately, I could run it in modelsim successfully. Now I am trying to use thr FFT IP instance inside my RTL design file, which when tried to run in modelsim for same version and license throws error as below:

///////////////////////////////////////////////////////////////////////////////////////////////////////////

# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L rtl_work -L work -L FFT -L FFT_altera_fft_ii_181 -voptargs=""+acc"" fft_interface_tb
# Start time: 10:26:05 on Mar 16,2021
# Loading sv_std.std
# Loading work.fft_interface_tb
# Loading work.fft_interface
# Loading FFT.FFT
# Loading FFT_altera_fft_ii_181.FFT_altera_fft_ii_181_rmnmcui
# ** Error: (vsim-3033) /<project_path>/fft_interface/FFT/altera_fft_ii_181/synth/FFT_altera_fft_ii_181_rmnmcui.sv(52): Instantiation of 'auk_dspip_r22sdf_top' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /fft_interface_tb/fft_interface_dut/FFT_dut/fft_ii_0 File: /<project_path>/fft_interface/FFT/altera_fft_ii_181/synth/FFT_altera_fft_ii_181_rmnmcui.sv
# Searched libraries:
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/altera
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/220model
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/sgate
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/altera_mf
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/altera_lnsim
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/twentynm
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/twentynm_hssi
# /opt/intelFPGA_PRO/modelsim_ase/altera/verilog/twentynm_hip
# /<project_path>/fft_interface/simulation/modelsim/rtl_work
# /<project_path>/fft_interface/simulation/modelsim/FFT_altera_fft_ii_181
# /<project_path>/fft_interface/simulation/modelsim/FFT
# /<project_path>/ip_test_rough/fft_interface/simulation/modelsim/FFT_altera_fft_ii_181
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fft_interface_run_msim_rtl_systemverilog.do PAUSED at line 22

//////////////////////////////////////////////////////////////////////////////////////////////////////

Please suggest what to do for this issue.

Regards

Susmita

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, you observe some issues when trying to simulate with the FFT IP. To facilitate further debugging, just would like to check with you on the following:


    1. As I understand it, you encounter issue when trying to simulate the IP in your design. Would you mind to further elaborate on the successful case where you "simulate the IP separately"? What is the difference between the passing vs failing case?


    2. By merely looking at the error message, it seems like one design unit was not found. This could be related to missing library or file during compilation. Just wonder if you have had a chance to look into if the 'auk_dspip_r22sdf_top' related source file is available and was compiled?


    3. What is the specific Quartus version that you are using?


    4. Are you running in Windows or Linux?


    Please let me know if there is any concern. Thank you.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.