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mamuneeb332
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3 years ago
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Facing issues with External Memory Interface IP with DDR4

Hello! I am trying to connect DDR4 with my Arria 10 FPGA with the help of EMIF IP. I had gone through the example design. I had followed the complete steps from Example Guide for building the examp...
mamuneeb332's avatar
mamuneeb332
Icon for New Contributor rankNew Contributor
3 years ago

Hello Sir,

I have been provided with references that allowed me to view the PNF bits in the Signal Tap Logic Analyzer. Additionally, I have obtained some data from the Efficiency Monitor using the EMIF Debug Toolkit (as shown in the attached snapshot). However, I am currently unable to determine the speed of data transfer between the FPGA and DDR4 memory, specifically the speed of reads or writes. I am seeking assistance in this matter. Please help me with this.

Thank you.