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mamuneeb332's avatar
mamuneeb332
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Facing issues with External Memory Interface IP with DDR4

Hello! I am trying to connect DDR4 with my Arria 10 FPGA with the help of EMIF IP. I had gone through the example design. I had followed the complete steps from Example Guide for building the examp...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

You can't use Signal Tap for this since those are hardened paths to the I/O. Enable the use of the EMIF Debug Toolkit in your example design to help test and debug that part of the interface.