Forum Discussion
mamuneeb332
New Contributor
New ContributorFacing issues with External Memory Interface IP with DDR4
Hello!
I am trying to connect DDR4 with my Arria 10 FPGA with the help of EMIF IP. I had gone through the example design. I had followed the complete steps from Example Guide for building the examp...
- All the info is here. You should have this bookmarked: https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html?wapkw=Memory%20support%20center
sstrell
Super Contributor
Super ContributorYou can't use Signal Tap for this since those are hardened paths to the I/O. Enable the use of the EMIF Debug Toolkit in your example design to help test and debug that part of the interface.
