Ethernet access via FPGA in DE10 nano board

I just checked with CHATGPT. Please confirm if this is the correct method.

To designate pins as "loaner I/O" for the HPS (Hard Processor System) in the DE10-Nano, follow these steps using the Quartus Prime software:

Step 1: Set Up the HPS Component in Qsys (Platform Designer)

1. Open Quartus Prime and your project.
2. Go to Tools > Platform Designer (formerly Qsys).
3. Add the HPS component to your design:
   • Click on the "Library" tab.
   • Search for "HPS" and add it to your system.

Step 2: Configure HPS Pins as Loaner I/O

1. In the HPS component configuration, navigate to the "Pin Mux" tab.
2. Find the peripherals or signals that you want to reassign as FPGA I/O (loaner I/O).
3. Disable the peripheral function for these pins by setting them to Loan I/O.
4. Once designated as loaner I/O, these pins are now available for use by the FPGA.

Step 3: Generate the HDL for HPS

1. Once the HPS configuration is complete, click on "Generate HDL" in the Platform Designer.
2. This will integrate the HPS into your FPGA design and make the loaner I/O pins available for assignment in the Pin Planner.