Error: (vcom-11) while running RTL simulation in Modelsim INTEL FPGA STARTER EDITION

Without even looking at your code, you have a space in your path ("VHDL Codes"). Modelsim doesn't like spaces in paths. Try removing the space.

Also, when you instantiate something, you should not have "work." in front of it. Remove that on line 55 of the testbench.