Forum Discussion

Miles1's avatar
Miles1
Icon for New Contributor rankNew Contributor
3 years ago

Error during synthesis of MAX 10 FPGA Development Kit sample project 'ddr3x24' in Quartus 20.1.1

I'm using the sample project 'ddr3x24' provided by the MAX 10 FPGA Development Kit. My Quartus version is 20.1.1. However, I'm getting the following error during synthesis. Can you please help me to ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


IP upgrade will update the IP that available in that particular Quartus version.

The newer Quartus version might have some new features added into the IP.

I have tried to replicate the issue at my end but I can successfully run the compilation after upgrading the IPs.


Are you not able to perform IP upgrade?


Regards,

Adzim


Miles1's avatar
Miles1
Icon for New Contributor rankNew Contributor
3 years ago

By the way, is this IP free of charge?

DDR3 SDRAM Controller with UniPHY Intel FPGA IP

Name

altera_mem_if_ddr3_emif

Version

20.1

Author

Altera Corporation

Description

DDR3 SDRAM Controller with UniPHY Intel FPGA IP