Forum Discussion

pmarques's avatar
pmarques
Icon for New Contributor rankNew Contributor
8 months ago
Solved

EMIF HPS errors after upgrading to Quartus 25.3

So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium De...
soc devkit
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    8 months ago

    Hello,

     

    Can you check in the design for pin placement of the user reference clock? Is it placed in Bank 3A?

     

    Can you check for the pin swizzling parameter in the EMIF HPS IP?

     

     

    Regards,

    Adzim

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
8 months ago

Hello,

 

Can you check in the design for pin placement of the user reference clock? Is it placed in Bank 3A?

 

Can you check for the pin swizzling parameter in the EMIF HPS IP?

 

 

Regards,

Adzim

pmarques's avatar
pmarques
Icon for New Contributor rankNew Contributor
8 months ago

Hello AdzimZM_Altera​,

Thanks for the pointers, it was indeed the pin swizzling and other parameters hidden inside the "Dive into Packaged Subsystem" of the EMIF HPS IP.

Initially after I upgraded the EMIF HPS IP, it appeared without any interfaces:

So I deleted the component and instantiated a new one but apparently caused all the hidden parameters to be reset. I was assuming these hidden parameters would be automatically set since Quartus knows I'm using a devkit.